1. Field of the Invention
The present invention relates to a semiconductor memory, especially a dynamic random access memory (DRAM), and more particularly, the present invention relates to a series of cell structures, arrangements, and activation schemes for high density, low power semiconductor memories.
2. Description of the Background
A conventional DRAM memory cell, consisting of one transistor and one capacitor (referred to as a 1T-1C configuration), is commonly used as a semiconductor memory when high bit density is required. This technology has several drawbacks and faces serious complications as device dimensions are scaled smaller. Most notably, since the DRAM cell has no internal gain, a high capacitance element (˜30 fF) must be fabricated in each cell to store a charge large enough to be adequately detected. Therefore, complex capacitor structures and expensive materials must be used to build a device with adequate capacitance, which leads to expensive fabrication and incompatibilities with standard logic processes.
In response to these limitations, small area gain cell memory technologies have been proposed. These are configured as 2- or 3-transistor cells in which a charge is stored in such a way that the conduction of a readout transistor is altered, thus providing internal gain. However, these technologies exhibit various problems that limit their widespread acceptance. Among these problems, cell size is still much larger than that of DRAM. This is due to the extra area used for additional transistors or spacing due to wire routing. For example, in many cells, two data and two word lines are necessary, limiting the cell size to twice the line pitch.
Other problems exhibited by gain cell technologies include short retention periods due to low storage capacitance and high leakage currents. In addition, driving and sensing schemes are often more complex than those found in conventional DRAM memories. Complex fabrication processes may be necessary for multi-transistor gain cells, further reducing the likelihood of their use as a replacement for DRAM.